(kicad_pcb
	(version 20241229)
	(generator "pcbnew")
	(generator_version "9.0")
	(general
		(thickness 1.6062)
		(legacy_teardrops no)
	)
	(paper "A4")
	(layers
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		(4 "In1.Cu" power "GNDU.Cu")
		(6 "In2.Cu" signal "SIGL.Cu")
		(2 "B.Cu" power "GNDL.Cu")
		(13 "F.Paste" user)
		(15 "B.Paste" user)
		(5 "F.SilkS" user "F.Silkscreen")
		(7 "B.SilkS" user "B.Silkscreen")
		(1 "F.Mask" user)
		(3 "B.Mask" user)
		(17 "Dwgs.User" user "User.Drawings")
		(25 "Edge.Cuts" user)
		(27 "Margin" user)
		(31 "F.CrtYd" user "F.Courtyard")
		(29 "B.CrtYd" user "B.Courtyard")
	)
	(setup
		(stackup
			(layer "F.SilkS"
				(type "Top Silk Screen")
				(color "White")
			)
			(layer "F.Paste"
				(type "Top Solder Paste")
			)
			(layer "F.Mask"
				(type "Top Solder Mask")
				(color "Green")
				(thickness 0.01)
			)
			(layer "F.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "dielectric 1"
				(type "prepreg")
				(thickness 0.2104)
				(material "FR4")
				(epsilon_r 4.4)
				(loss_tangent 0.02)
			)
			(layer "In1.Cu"
				(type "copper")
				(thickness 0.0152)
			)
			(layer "dielectric 2"
				(type "core")
				(thickness 1.065)
				(material "FR4")
				(epsilon_r 4.6)
				(loss_tangent 0.02)
			)
			(layer "In2.Cu"
				(type "copper")
				(thickness 0.0152)
			)
			(layer "dielectric 3"
				(type "prepreg")
				(thickness 0.2104)
				(material "FR4")
				(epsilon_r 4.4)
				(loss_tangent 0.02)
			)
			(layer "B.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "B.Mask"
				(type "Bottom Solder Mask")
				(color "Green")
				(thickness 0.01)
			)
			(layer "B.Paste"
				(type "Bottom Solder Paste")
			)
			(layer "B.SilkS"
				(type "Bottom Silk Screen")
				(color "White")
			)
			(copper_finish "ENIG")
			(dielectric_constraints yes)
		)
		(pad_to_mask_clearance 0)
		(allow_soldermask_bridges_in_footprints no)
		(tenting front back)
		(pcbplotparams
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			(pdf_back_fp_property_popups yes)
			(pdf_metadata yes)
			(pdf_single_document no)
			(dxfpolygonmode yes)
			(dxfimperialunits yes)
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			(plot_black_and_white yes)
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			(subtractmaskfromsilk no)
			(outputformat 1)
			(mirror no)
			(drillshape 1)
			(scaleselection 1)
			(outputdirectory "")
		)
	)
	(net 0 "")
	(net 1 "Net-(C1-Pad2)")
	(net 2 "/I_FARADAY")
	(net 3 "GND")
	(net 4 "+2V5")
	(net 5 "+24V")
	(net 6 "Net-(U1B-+)")
	(net 7 "+5VA")
	(net 8 "-5VA")
	(net 9 "/SIG_OUT")
	(net 10 "/RANGE")
	(net 11 "Net-(Q2-C)")
	(net 12 "Net-(Q3-B)")
	(net 13 "Net-(K1-Pad10)")
	(net 14 "Net-(Q1-D)")
	(net 15 "Net-(K1-Pad1)")
	(net 16 "Net-(U1B--)")
	(net 17 "Net-(C2-Pad2)")
	(footprint "PCM_JLCPCB:D_SOD-323"
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